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ASAHI KASEI
[AK4631]
AK4631
16-Bit Mono CODEC with ALC & MIC/SPK-AMP
AK4631 ALC(Automatic Level Control) QFN 16bit CODEC DSC 28pin
1. 16-Bit Delta-Sigma Mono CODEC 2. * 1ch Mono Input * (0dB, 20dB, 26dB or 32dB) * ALC IPGA (-8dB +27.5dB, 0.5dB Step) * ADC : S/(N+D) : 80dB, DR, S/N : 85dB 3. * Digital Volume (+12dB -115dB, 0.5dB Step, Mute) * Mono Line Output: S/(N+D) : 85dB, S/N : 93dB * Mono Speaker-Amp - SPK-AMP : S/(N+D) : 50dB, S/N : 90dB (240mW@ 8, ) - BTL - ALC(Automatic Level Control) : 250mW @ 8&SVDD=3.3V 3.0Vrms@SVDD=5V * Beep 4. 5. PLL Mode: * : 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (FCK pin) 16fs, 32fs or 64fs (BICK pin) 6. EXT Mode: * : 256fs, 512fs or 1024fs (MCKI pin) 7. Sampling Rate: * PLL Slave Mode (FCK pin) : 7.35kHz ~ 26kHz * PLL Slave Mode (BICK pin) : 7.35kHz ~ 48kHz * PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz * PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz * EXT Slave Mode: 7.35kHz ~48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~13kHz (1024fs) 8. Output Master Clock Frequency: 256fs 9. P :3 10. /
MS0317-J-01 -1-
2004/11
ASAHI KASEI
[AK4631]
11. Audio Interface Format: MSB First, 2's compliment * ADC: DSP Mode, 16bit , I2S * DAC: DSP Mode, 16bit , , I2S 12. Ta = -10 70C 13. * CODEC: 2.6 3.6V (typ. 3.3V) * Speaker-Amp : 2.6 5.25V (typ. 3.3V/5.0V) 14. : 16 mA 15. Package: 28pin QFN 16. AK4536/AK4630
AVSS AVDD MICOUT MPI MIC
MIC-AMP 0dB or 20dB or 26dB or 32dB PMMIC MIC Power Supply ALC1 (IPGA) PMADC
AIN
ADC
HPF
PDN
Audio
PMAO ALC1A DACA PMDAC
FCK BICK
Interface DVOL
AOUT
BEEPA DACM ALC1M
DAC
SDTO SDTI
SVDD SVSS
PMSPK
DSP and uP
SPP
SPKAMP
SPN
MIX
ALC2 Control Register
PMBP
CSN CCLK CDTI
PMPLL
MCKO
PLL
MCKI VCOM BEEP DVSS DVDD MIN MOUT VCOC
Figure 1. AK4631 Block Diagram
MS0317-J-01 -2-
2004/11
ASAHI KASEI
[AK4631]
AK4631VN AKD4631
-10 +70C AK4631
28pin QFN (0.5mm pitch)
MICOUT
28
27
26
25
24
23
VCOM AVSS AVDD VCOC PDN CSN CCLK
22
MOUT
AOUT
BEEP
MIC
MPI
AIN
1 2 3 4 5 6 10 11 12 13 7 8 9
21 20 19
MIN SVSS SVDD SPN SPP MCKO MCKI
Top View
18 17 16 14 15
DVDD
SDTO
MS0317-J-01 -3-
DVSS
BICK
CDTI
SDTI
FCK
2004/11
ASAHI KASEI
[AK4631]
AK4536, AK4630
AK4536, AK4630 AK4536 1. AK4536VN AVDD, DVDD, SVDD SPK-Amp ALC2 OFF AVDD=DVDD=SVDD=3.3V 2.4V 3.6V 2 150mW@8 250mW@8 AK4630VN 2.4V 3.6V 2 150mW@8 250mW@8 AK4631VN 2.6V 3.6V 4 150mW@8 250mW@8 250mW 250mW 2 150mW@8 240mW@8 2.6V 3.6V 2.6V 5.25V 4 AK4630 AK4631
+4.2dB +6.2dB
SPK-Amp ALC2 ON AVDD=DVDD=SVDD=3.3V AVDD, DVDD SVDD SPK-Amp
2 150mW@8 250mW@8
2 150mW@8 250mW@8
MCKI pin AC Coupling ALC2 +18dB 7.35kHz 26kHz 0dB/+20dB 1 1061/fs 11.2896MHz, 12MHz, 12.288MHz +18dB 7.35kHz 26kHz 0dB/+20dB 1 1061/fs 11.2896MHz, 12MHz, 12.288MHz +19.5dB-12.0dB 7.35kHz 48kHz 0dB/+20dB/+26dB/+32dB 2 1061/fs, 256/fs 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz AVSS +7.84 dB SPKG1-0 bits = "00" 6.8k + 220nF
MIC Amp PLL AOUT AOUT pin BEEP SPP/SPN ( = 20k ) PLL FCK VCOC RC PLL Master Mode Audio I/F Format PLL Slave Mode Audio I/F Format PLL Master Mode FCK "H" (Note 1 ) Min
Hi-Z +6dB SPKG bit = "0" 10k + 470nF DSP Mode DSP Mode 1 / tBCK 0.2
+0.10 -0.20
Hi-Z +6dB SPKG bit = "0" 10k + 470nF
50% duty 0.55 0.20 mm 0.70 mm
50% duty 0.55 0.20 mm 0.70 mm
mm
0.80 mm 0.78 +0.17
-0.28
MS0317-J-01 -4-
2004/11
ASAHI KASEI
[AK4631]
AK4536VN Mono Line Output D-Range (typ) S/N(typ) Speaker-Amp Output Voltage (-0.5dBFS ) SPKG1-0 bits = "00" (typ) SPKG1-0 bits = "01" (typ) S/(N+D) (240mW ) SPKG1-0 bits ="01" (typ) S/(N+D) (250mW ) SPKG1-0 bits ="01" (typ) ADC Digital Filter (HPF) : fs=8kHz Frequency Response -3.0dB (typ) -0.5dB -0.1dB Note 1. AK4631 AK4536 95dB 95dB
AK4630VN 95dB 95dB
AK4631VN 93dB 93dB
2.92Vpp 3.78Vpp 50dB 1.25Hz 3.56 Hz 8.14 Hz
2.92Vpp 3.78Vpp 50dB 1.25 Hz 3.56 Hz 8.14 Hz
3.09Vpp 3.92Vpp 50dB 20dB 0.62 Hz 1.81 Hz 3.99 Hz
2. AK4536VN MCKI / XTI XTO AK4630VN MCKI MCKO AK4631VN MCKI MCKO
# 15 # 16
MS0317-J-01 -5-
2004/11
ASAHI KASEI
[AK4631]
3. (1)
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Input PGA Control Digital Volume Control ALC2 Mode Control D7 0 0 SPPS 0 PLL3 0 DVTM 0 0 0 DVOL7 0 D6 PMVCM 0 BEEPS AOPSN PLL2 0 ROTM ALC2 REF6 IPGA6 DVOL6 0 AK4536 AK4536 D5 PMBP 0 ALC2S MGAIN1 PLL1 FS3 ZTM1 ALC1 REF5 IPGA5 DVOL5 RFS5 AK4630 AK4630 D4 PMSPK 0 DACA SPKG1 PLL0 MSBS ZTM0 ZELM REF4 IPGA4 DVOL4 RFS4 D3 PMAO M/S DACM SPKG0 BCKO1 BCKP WTM1 LMAT1 REF3 IPGA3 DVOL3 RFS3 D2 PMDAC MCKPD MPWR BEEPA BCKO0 FS2 WTM0 LMAT0 REF2 IPGA2 DVOL2 RFS2 D1 PMMIC MCKO MICAD ALC1M DIF1 FS1 LTM1 RATT REF1 IPGA1 DVOL1 RFS1 D0 PMADC PMPLL MGAIN0 ALC1A DIF0 FS0 LTM0 LMTH REF0 IPGA0 DVOL0 RFS0
(2) MCKO bit (Addr = 01H, D1 bit) AK4536 Addr = 01H, D1 PMXTL bit AK4630/AK4631 MCKO bit 0: "L" output (Default) 1: 256fs output
(3) FS1-0 bits (Addr = 05H, D1-0 bits) FCK or BICK PLL (PLL2 bit = "0" and PMPLL bit = "1") FS3-0 bits
Sampling Frequency Range Mode FS3 bit FS2 bit FS1 bit FS0 bit AK4536/AK4630 AK4631 0 Don't care 0 0 0 7.35kHz fs 10kHz 7.35kHz fs 8kHz 0 Don't care 1 1 0 10kHz < fs 14kHz 8kHz < fs 12kHz 0 Don't care 0 2 1 14kHz < fs 20kHz 12kHz < fs 16kHz 0 Don't care 1 3 1 20kHz < fs 26kHz 16kHz < fs 24kHz 1 Don't care 0 N/A 6 1 24kHz < fs 32kHz 1 Don't care 1 N/A 7 1 32kHz < fs 48kHz Others Others N/A N/A 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz AK4536/AK4630 AK4631
MS0317-J-01 -6-
2004/11
ASAHI KASEI
[AK4631]
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin Name VCOM AVSS AVDD VCOC PDN CSN CCLK CDTI SDTI SDTO FCK BICK DVDD DVSS MCKI MCKO SPP SPN SVDD SVSS MIN MOUT AOUT BEEP AIN MICOUT MIC MPI
I/O O O I I I I I O I/O I/O I O O O I O O I I O I O
Function Common Voltage Output Pin, 0.45 x AVDD Bias voltage of ADC inputs and DAC outputs. Analog Ground Pin Analog Power Supply Pin Output Pin for Loop Filter of PLL Circuit This pin should be connected to AVSS with one resistor and capacitor in series. Power-Down Mode Pin "H": Power up, "L": Power down reset and initialize the control register. Chip Select Pin Control Data Clock Pin Control Data Input Pin Audio Serial Data Input Pin Audio Serial Data Output Pin Frame Clock Pin Audio Serial Data Clock Pin Digital Power Supply Pin Digital Ground Pin External Master Clock Input Pin (Internal Pull Down 25k@PDN pin ="L") Master Clock Output Pin Speaker Amp Positive Output Pin Speaker Amp Negative Output Pin Speaker Amp Power Supply Pin Speaker Amp Ground Pin ALC2 Input Pin Mono Analog Output Pin Mono Line Output Pin Beep Signal Input Pin IPGA (ALC1) Input Pin Microphone Analog Output Pin Microphone Input Pin (Mono Input) MIC Power Supply Pin for Microphone
Note: All input pins except analog input pins (MIC, AIN, MIN and BEEP pins) should not be left floating.
Classification Analog Input Analog Output Digital Input Digital Output
Pin Name MIC, AIN, BEEP, MIN MICOUT, MPI, AOUT, MOUT, SPP, SPN MCKI, SDTI, FCK(when M/S bit = "0"), BICK(when M/S bit = "0") MCKO, SDTO, FCK(when M/S bit = "1"), BICK(when M/S bit = "1") DVSS
MS0317-J-01 -7-
2004/11
ASAHI KASEI
[AK4631]
(AVSS, DVSS, SVSS=0V; Note 2) Parameter Power Supplies: Analog Digital Speaker-Amp |AVSS - DVSS| (Note 3) |AVSS - SVSS| (Note 3) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (powered applied) Storage Temperature Maximum Power Dissipation (Note 4) Note 2. Note 3. AVSS Note 4.
Symbol AVDD DVDD SVDD GND1 GND2 IIN VINA VIND Ta Tstg Pd
min -0.3 -0.3 -0.3 -0.3 -0.3 -10 -65 -
max 6.0 6.0 6.0 0.3 0.3 10 AVDD+0.3 DVDD+0.3 70 150 520
Units V V V V V mA V V C C mW
DVSS, SVSS 100% AK4631
:
(AVSS, DVSS, SVSS=0V; Note 2) Parameter Power Supplies Analog (Note 5) Digital Speaker-Amp (Note 6) Difference Note 2. Note 5. AVDD, DVDD, SVDD OFF Note 6. 8
Symbol AVDD DVDD SVDD AVDD-DVDD
min 2.6 2.6 2.6 -0.3
typ 3.3 3.3 3.3 / 5.0 0
max 3.6 3.6 5.25 0.3
Units V V V V
ON PDN pin = "L" SVDD = 2.6V 3.6V
:
MS0317-J-01 -8-
2004/11
ASAHI KASEI
[AK4631]
(Ta=25C; AVDD, DVDD, SVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 3.4kHz; EXT Slave Mode; unless otherwise specified) Parameter min typ max Units MIC Amplifier Input Resistance 20 30 40 k Gain (MGAIN1-0 bits = "00") 0 dB (MGAIN1-0 bits = "01") 20 dB (MGAIN1-0 bits = "10") 26 dB (MGAIN1-0 bits = "11") 32 dB MIC Power Supply: MPI pin Output Voltage (Note 7) 2.22 2.47 2.72 V Load Resistance 2 k Load Capacitance 30 pF Input PGA Characteristics: Input Resistance (Note 8) 5 10 15 k Step Size 0.05 0.5 0.9 dB Gain Control Range +27.5 dB -8 ADC Analog Input Characteristics: MIC IPGA ADC, MIC Gain=20dB, IPGA=0dB, ALC1=OFF Resolution 16 Bits Input Voltage (MIC Gain=20dB, Note 9) 0.168 0.198 0.228 Vpp 68 80 dB S/(N+D) (-1dBFS) (Note 10) 75 85 dB D-Range (-60dBFS) S/N 75 85 dB DAC Characteristics: Resolution 16 Bits Mono Line Output Characteristics: AOUT pin, DAC AOUT, RL=10k 1.78 1.98 2.18 Vpp Output Voltage (Note 11) 73 85 dB S/(N+D) (0dBFS) (Note 10) 83 93 dB D-Range (-60dBFS) 83 93 dB S/N 10 Load Resistance k 30 pF Load Capacitance Speaker-Amp Characteristics: MIN SPP/SPN pins, ALC2=OFF, RL=8, BTL, SVDD=3.3V Output Voltage SPKG1-0 bits = "00" (-0.5dBFS) 2.47 3.09 3.71 Vpp (Note 12) SPKG1-0 bits = "01" (-0.5dBFS) 3.10 3.92 4.74 Vpp 40 60 dB SPKG1-0 bits ="00" (150mW ) S/(N+D) 20 50 dB SPKG1-0 bits ="01" (240mW ) 20 dB SPKG1-0 bits ="01" (250mW ) 80 90 dB S/N (Note 14) Load Resistance 8 30 pF Load Capacitance Speaker-Amp Characteristics: MIN SPP/SPN pins, ALC2=OFF, CL=3F, Rserial=10 x 2, BTL, SVDD=5.0V Output Voltage SPKG1-0 bits = "10" (0dBFS) 6.72 Vpp (Note 12) SPKG1-0 bits = "11" (0dBFS) 6.80 8.50 10.20 Vpp S/(N+D) (Note 12) SPKG1-0 bits = "10" (0dBFS) 60 dB (Note 13) SPKG1-0 bits = "11" (0dBFS) 20 50 dB 80 90 dB S/N (Note 13) (Note 14) Load Impedance (Note 15) 50 3 Load Capacitance F
MS0317-J-01 -9-
2004/11
ASAHI KASEI
[AK4631]
Parameter min typ BEEP Input: BEEP pin, External Input Resistance= 20k Maximum Input Voltage (Note 16) 1.98 Output Voltage (Input Voltage=0.6Vpp) 0.74 1.48 BEEP SPP/SPN (SPKG1-0 bits = "00") 0.3 0.6 BEEP AOUT Mono Input: MIN pin 2.18 Maximum Input Voltage (Note 17) 12 24 Input Resistance (Note 18) Mono Output: MOUT pin, DAC MOUT 1.78 1.98 Output Voltage (Note 19) Load Resistance 10 Load Capacitance Power Supplies Power Up (PDN = "H") All Circuit Power-up: (Note 20) AVDD+DVDD fs=8kHz 9 fs=48kHz 11.5 SVDD: Speaker-Amp Normal Operation (SPPS bit = "1", No Output) SVDD=3.3V 7 SVDD=5.0V 9 Power Down (PDN = "L") 10 AVDD+DVDD+SVDD
max 2.22 0.9 36 2.18 30
Units Vpp Vpp Vpp Vpp k Vpp k pF
17.5 27 200
mA mA mA mA A
Note 7. AVDD Vout = 0.75 x AVDD (typ) Note 8. IPGA ALC1 typ.8k11k Note 9. AVDD Vin = 0.06 x AVDD (typ) Note 10. PLL Slave Mode FCK pin PLL S/(N+D) 77dB(typ) Note 11. AVDD Vout = 0.6 x AVDD (typ) Note 12. MIN = 1.98Vpp Note 13. SPP pin /SPN pin Note 14. SPKG1-0 bits Note 15. Figure 34 Load Impedance 1kHz Load Capacitance SPP, SPN pin 10 Note 16. AVDD (Rin) Vout = 0.6 x AVDD x Rin/20k(max) Note 17. AVDD Vin = 0.66 x AVDD (max) Note 18. Mono Input ALC2 typ.22k26k Note 19. AVDD Vout = 0.6 x AVDD (typ) Note 20. PLL Master Mode (MCKI=12.288MHz) PMMIC = PMADC = PMDAC = PMSPK = PMVCM = PMPLL = MCKO = PMAO = PMBP = MPWR = M/S ="1" MPI pin 0mA EXT (PMPLL=MCKO=M/S= "0") AVDD+DVDD = 7mA (fs=8kHz, typ) 9.5mA (fs=48kHz, typ)
MS0317-J-01 - 10 -
2004/11
ASAHI KASEI
[AK4631]
(Ta = 25C; AVDD, DVDD =2.6 3.6V, SVDD =2.6 5.25V; fs=8kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): 0.16dB PB 0 Passband (Note 21) -0.66dB -1.1dB -6.9dB Stopband (Note 21) SB 4.7 Passband Ripple PR Stopband Attenuation SA 73 Group Delay (Note 22) GD Group Delay Distortion GD ADC Digital Filter (HPF): Frequency Response (Note 21) -3.0dB FR -0.5dB -0.1dB DAC Digital Filter: Passband (Note 21) 0.1dB PB 0 -0.7dB -6.0dB Stopband (Note 21) SB 4.6 Passband Ripple PR Stopband Attenuation SA 59 Group Delay (Note 22) GD DAC Digital Filter + Analog Filter: Frequency Response: 0 3.4kHz FR Note 21. Note 22. DAC fs ( ADC PB=3.6kHz (@-1.0dB) 0.45 x fs ADC 16 )
typ
max 3.0 0.1
Units kHz kHz kHz kHz kHz dB dB 1/fs s Hz Hz Hz kHz kHz kHz dB dB 1/fs dB
3.5 3.6 4.0
17.1 0 0.62 1.81 3.99 3.6 0.01 16.8 1.0
3.6 4.0
1kHz 16
DC (Ta = 25C; AVDD, DVDD =2.6 3.6V, SVDD =2.6 5.25V) Parameter Symbol High-Level Input Voltage VIH Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-80A) VOH Low-Level Output Voltage (Iout= 80A) VOL Input Leakage Current Iin
min 70%DVDD DVDD-0.4 -
typ -
max 30%DVDD 0.4 10
Units V V V V A
MS0317-J-01 - 11 -
2004/11
ASAHI KASEI
[AK4631]
(Ta = 25C; AVDD, DVDD =2.6 3.6V, SVDD =2.6 5.25V; CL=20pF) Parameter Symbol min PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2) MCKI Input: Frequency Pulse Width Low Pulse Width High MCKO Output: Frequency Duty Cycle except fs=29.4kHz,32kHz fs=29.4kHz, 32kHz (Note 23) FCK Output: Frequency Duty Cycle BICK: Period (BCKO1-0 = "00") (BCKO1-0 = "01") (BCKO1-0 = "10") Duty Cycle Audio Interface Timing DSP Mode: (Figure 3, Figure 4) FCK "" to BICK "" (Note 24) FCK "" to BICK "" (Note 25) BICK "" to SDTO (BCKP = "0") BICK "" to SDTO (BCKP = "1") SDTI Hold Time SDTI Setup Time Except DSP Mode: (Figure 5) BICK "" to FCK Edge FCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO SDTI Hold Time SDTI Setup Time fCLK tCLKL tCLKH fMCK dMCK dMCK fFCK dFCK tBCK tBCK tBCK dBCK 11.2896 0.4/fCLK 0.4/fCLK
typ
max 27.0
Units MHz ns ns kHz % % kHz % ns ns ns %
40 8
256 x fFCK 50 33 50 1/16fFCK 1/32fFCK 1/64fFCK 50
60 48
tDBF tDBF tBSD tBSD tSDH tSDS tBFCK tFSD tBSD tSDH tSDS
0.5 x tBCK -40 0.5 x tBCK -40 -70 -70 50 50 -40 -70 -70 50 50
0.5 x tBCK 0.5 x tBCK
0.5 x tBCK + 40 0.5 x tBCK +40 70 70
ns ns ns ns ns ns ns ns ns ns ns
40 70 70
MS0317-J-01 - 12 -
2004/11
ASAHI KASEI
[AK4631]
Parameter Symbol min PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 6, Figure 7) FCK: Frequency DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle BICK: Period Pulse Width Low Pulse Width High FCK: Frequency DSP Mode: Pulse width High Except DSP Mode: Duty Cycle BICK: Period (PLL3-0 = "0001") (PLL3-0 = "0010") (PLL3-0 = "0011") Pulse Width Low Pulse Width High MCKI Input: Frequency Pulse Width Low Pulse Width High MCKO Output: Frequency Duty Cycle except fs=29.4kHz, 32kHz fs=29.4kHz, 32kHz (Note 23) FCK: Frequency DSP Mode: Pulse width High Except DSP Mode: Duty Cycle BICK: Period Pulse Width Low Pulse Width High Audio Interface Timing DSP Mode: (Figure 9, Figure 10) FCK "" to BICK "" (Note 24) FCK "" to BICK "" (Note 25) BICK "" to FCK "" (Note 24) BICK "" to FCK "" (Note 25) BICK "" to SDTO (BCKP = "0") BICK "" to SDTO (BCKP = "1") SDTI Hold Time SDTI Setup Time Except DSP Mode: (Figure 12) FCK Edge to BICK "" (Note 26) BICK "" to FCK Edge (Note 26) FCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO SDTI Hold Time SDTI Setup Time fFCK tFCKH duty tBCK tBCKL tBCKH fFCK tFCKH duty tBCK tBCK tBCK tBCKL tBCKH fCLK fCLKL fCLKH fMCK dMCK dMCK fFCK tFCKH duty tBCK tBCKL tBCKH 7.35 tBCK-60 45 1/64fFCK 240 240 7.35 tBCK-60 45
typ 8
max 26 1/fFCK-tBFCK 55 1/16fFCK
Units kHz ns % ns ns ns kHz ns % ns ns ns ns ns MHz ns ns kHz % % kHz ns % ns ns ns
PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 6, Figure 7) 8 48 1/fFCK-tBFCK 55
1/16fFCK 1/32fFCK 1/64fFCK 0.4 x tBCK 0.4 x tBCK 11.2896 0.4/fCLK 0.4/fCLK 256 x fFCK 50 33 27.0
PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 8)
40 8 tBCK-60 45 1/64fFCK 0.4 x tBCK 0.4 x tBCK
60 48 1/fFCK-tBFCK 55 1/16fFCK
tFCKB tFCKB tBFCK tBFCK tBSD tBSD tSDH tSDS tFCKB tBFCK tFSD tBSD tSDH tSDS
0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 80 80 50 50 50 50 80 80 50 50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MS0317-J-01 - 13 -
2004/11
ASAHI KASEI
[AK4631]
Parameter EXT Slave Mode (Figure 11) MCKI Frequency: 256fs 512fs 1024fs Pulse Width Low Pulse Width High FCK Frequency (MCKI = 256fs) (MCKI = 512fs) (MCKI = 1024fs) Duty Cycle BICK Period BICK Pulse Width Low Pulse Width High Audio Interface Timing (Figure 12) FCK Edge to BICK "" (Note 26) BICK "" to FCK Edge (Note 26) FCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO SDTI Hold Time SDTI Setup Time
Symbol fCLK fCLK fCLK tCLKL tCLKH fFCK fFCK fFCK duty tBCK tBCKL tBCKH tFCKB tBFCK tFSD tBSD tSDH tSDS
min 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK 7.35 7.35 7.35 45 312.5 130 130 50 50
typ 2.048 4.096 8.192
max 12.288 13.312 13.312
Units MHz MHz MHz ns ns kHz kHz % ns ns ns ns ns ns ns ns ns
8 8 8
48 26 13 55
80 80 50 50
Note 23. Duty Cycle = "L " / x 100 Note 24. MSBS, BCKP bits = "00" or "11" Note 25. MSBS, BCKP bits = "01" or "10" Note 26. FCK BICK ""
Parameter Control Interface Timing: CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" Reset Timing PDN Pulse Width PMADC "" to SDTO valid (Note 27) (Note 28)
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tPD tPDV
min 200 80 80 40 40 150 150 50 150
typ
max
Units ns ns ns ns ns ns ns ns ns 1/fs
1059
Note 27. AK4631 PDN pin = "L" Note 28. PMADC bit
FCK
""
MS0317-J-01 - 14 -
2004/11
ASAHI KASEI
[AK4631]
1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fFCK
FCK dFCK 1/fMCK dFCK
50%DVDD
MCKO tMCKOH tMCKOL
50%DVDD
dMCK = tMCKOL x fMCK x 100
Figure 2. Clock Timing (PLL Master mode)
FCK tDBF tBCK dBCK BICK (BCKP = "0")
50%DVDD
50%DVDD
BICK (BCKP = "1") tBSD SDTO
50%DVDD
MSB
50%DVDD
tSDS
tSDH VIH MSB VIL
SDTI
Figure 3. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = "0")
MS0317-J-01 - 15 -
2004/11
ASAHI KASEI
[AK4631]
FCK tDBF tBCK dBCK BICK (BCKP = "1")
50%DVDD
50%DVDD
BICK (BCKP = "0") tBSD SDTO
50%DVDD
MSB
50%DVDD
tSDS
tSDH VIH VIL
SDTI
MSB
Figure 4. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = "1")
FCK
50%DVDD
tBFCK
dBCK 50%DVDD
BICK tFSD
tBSD
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Figure 5. Audio Interface Timing (PLL Master mode & Except DSP mode)
MS0317-J-01 - 16 -
2004/11
ASAHI KASEI
[AK4631]
1/fFCK VIH VIL tFCKH tBCK VIH BICK (BCKP = "0") tBCKH tBCKL VIH BICK (BCKP = "1") VIL VIL tBFCK
FCK
Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 0)
1/fFCK VIH VIL tFCKH tBCK VIH BICK (BCKP = "1") tBCKH tBCKL VIH BICK (BCKP = "0") VIL VIL tBFCK
FCK
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1)
MS0317-J-01 - 17 -
2004/11
ASAHI KASEI
[AK4631]
1/fCLK VIH MCKI VIL tCLKH 1/fFCK VIH FCK VIL tFCKH tBCK VIH BICK VIL tBCKH 1/fMCK tBCKL tFCKL tCLKL
MCKO tMCKOH tMCKOL
50%DVDD
dMCK = tMCKOL x fMCK x 100
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)
MS0317-J-01 - 18 -
2004/11
ASAHI KASEI
[AK4631]
tFCKH VIH FCK tFCKB VIL
VIH BICK (BCKP = "0") VIH BICK (BCKP = "1") tBSD VIL VIL
SDTO
MSB tSDH
50%DVDD
tSDS
VIH SDTI MSB VIL
Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0)
tFCKH VIH FCK tFCKB VIL
VIH BICK (BCKP = "1") VIH BICK (BCKP = "0") tBSD VIL VIL
SDTO
MSB
50%DVDD
tSDS
tSDH VIH
SDTI
MSB
VIL
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1) MS0317-J-01 - 19 2004/11
ASAHI KASEI
[AK4631]
1/fCLK VIH MCKI tCLKH 1/fFCK VIH FCK tFCKH tBCK VIH VIL tBCKH tBCKL tFCKL VIL tCLKL VIL
BICK
Figure 11. Clock Timing (EXT Slave mode)
VIH FCK VIL tBFCK tFCKB VIH BICK VIL tFSD tBSD
SDTO tSDS
MSB tSDH
50%DVDD
VIH SDTI VIL
Figure 12. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode)
MS0317-J-01 - 20 -
2004/11
ASAHI KASEI
[AK4631]
VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCCK tCDH VIH R/W VIL
Figure 13. WRITE Command Input Timing
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI D2 D1 D0 VIL
Figure 14. WRITE Data Input Timing
VIH CSN VIL tPDV
SDTO
50%DVDD
Figure 15. Power Down & Reset Timing 1
tPD PDN VIL
Figure 16. Power Down & Reset Timing 2
MS0317-J-01 - 21 -
2004/11
ASAHI KASEI
[AK4631]
I/F
4
See Table 1 and Table 2 MCKPD bit 0 0 1 0 X Figure Figure 18 Figure 19 Figure 20 Figure 21 -
Mode PMPLL bit M/S bit PLL3-0 bit PLL Master Mode 1 1 See Table 4 PLL Slave Mode 1 1 0 See Table 4 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 1 0 See Table 4 (PLL Reference Clock: FCK or BICK pin) EXT Slave Mode 0 0 X Don't Care (Note 29) 0 1 X Table 1. Clock Mode Setting (X: Don't care) Note 29.
MCKO, FCK, BICK
Mode PLL Master Mode
MCKO bit 0 1
MCKO pin "L" Output 256fs Output "L" Output 256fs Output "L" Output
MCKI pin Master Clock Input for PLL (Note 30) Master Clock Input for PLL (Note 30) GND
BICK pin 16fs/32fs/64fs Output 16fs/32fs/64fs Input 16fs/32fs/64fs Input
FCK pin 1fs Output 1fs Input 1fs Input 1fs Input
PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL Reference Clock: FCK or BICK pin) EXT Slave Mode
0 1 0
256fs/ 512fs/ 32fs 0 "L" Output 1024fs Input Input Note 30. 11.2896MHz/12MHz/12.288MHz/13.5MHz/24MHz/27MHz Table 2. Clock pins state in Clock Mode ] MCKPD bit = "0" (typ)
[MCKI
MCKPD
bit = "1" (Default)
25k
MCKI
MCKPD bit ="0"
25k
AK4631
Figure 17. Pull-down resistor of MCKI pin
MS0317-J-01 - 22 -
2004/11
ASAHI KASEI
[AK4631]
AK4631 M/S bit "1"
M/S bit (PDN pin = "L") M/S bit "1" AK4631 FCK, BICK pin
"1"
"0"
AK4631 100k
FCK, BICK pin
M/S bit Mode 0 Slave Mode 1 Master Mode Table 3. Select Master/Salve Mode
Default
PLL
PMPLL bit = "1" PLL PLL FS3-0 bit, PLL3-0 bit PMPLL bit "0" "1" Table 4
1) PLL Mode
Mode
PLL3 bit 0 0 0 0 0 0 0 0 1 1
PLL2 bit 0 0 0 0 1 1 1 1 1 1
Others
PLL1 bit 0 0 1 1 0 0 1 1 0 0
PLL0 bit 0 1 0 1 0 1 0 1 0 1
PLL
0 1 2 3 4 5 6 7 12 13
Others
FCK pin 1fs BICK pin 16fs BICK pin 32fs BICK pin 64fs MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz N/A Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
VCOC pin R,C R[] C[F] 6.8k 220n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n
PLL (max) 160ms 2ms 2ms 2ms 40ms 40ms 40ms 40ms 40ms 40ms
Default
2) PLL Mode PLL2 bit = "1" (MCKI ) Table 5 Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 5. Setting of Sampling Frequency at PLL2 bit = "1" and PMPLL bit = "1"
Default
MS0317-J-01 - 23 -
2004/11
ASAHI KASEI
[AK4631]
PLL2 bit = "0" Table 6
(FCK or BICK
)
FS3, FS1-0 bit
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 Don't care 0 0 0 7.35kHz fs 8kHz 0 Don't care 1 1 0 8kHz < fs 12kHz 0 Don't care 0 2 1 12kHz < fs 16kHz 0 Don't care 1 3 1 16kHz < fs 24kHz 1 Don't care 0 6 1 24kHz < fs 32kHz 1 Don't care 1 7 1 32kHz < fs 48kHz Others Others N/A Table 6. Setting of Sampling Frequency at PLL2 bit = "0" and PMPLL bit = "1" (Note) FCK (PLL3-0 bits = "0000") 7.35kHz fs 26kHz
Default
PLL
1) PLL Master Mode (PMPLL bit = "1", M/S bit = "1") PMPLL bit = "0" MCKO FCK BICK "L" MCKO bit = "0" "1" PLL MCKO bit = "1" MCKO "L" 1 FCK, BICK, MCKO (See Table 7) FCK, BICK
PLL
BICK
FCK 1fs
"L"
MCKO pin BICK pin FCK pin MCKO bit = "0" MCKO bit = "1" "L" Output PMPLL bit "0" "1" "L" Output "L" Output "L" Output PLL Unlock "L" Output 256fs Output 1fs Output See Table 9 PLL Lock Table 7. Clock Operation at PLL Master Mode (PMPLL bit = "1", M/S bit = "1") PLL State 2) PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") PMPLL bit = "0" PLL Addr=02H "1" PLL ADC DAC "0" MCKO 256fs MCKO
DAC
DACA bit
DACM bit
MCKO pin MCKO bit = "0" MCKO bit = "1" "L" Output PMPLL bit "0" "1" "L" Output PLL Unlock "L" Output 256fs Output PLL Lock Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = "0", M/S bit = "0") PLL State
MS0317-J-01 - 24 -
2004/11
ASAHI KASEI
[AK4631]
PLL Master Mode (PMPLL bit = "1", M/S bit = "1") 11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz MCKO, BICK, FCK MCKO 256fs BICK BCKO1-0 bit 16fs, 32fs or 64fs BICK 16fs I/F DSP
11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz
MCKO bit
PLL ON/OFF (See Table 9)
AK4631
MCKI MCKO BICK FCK SDTO SDTI 256fs 16fs, 32fs, 64fs 1fs
DSP or P
MCLK BCLK FCK SDTI SDTO
Figure 18. PLL Master Mode
Mode 0 1 2 3
BCKO0 BCKO1 BICK 0 0 16fs 0 1 32fs 1 0 64fs 1 1 N/A Table 9. BICK Output Frequency at Master Mode
Default
MS0317-J-01 - 25 -
2004/11
ASAHI KASEI
[AK4631]
PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") MCKI, BICK or FCK pin PLL I/F DSP a) PLL FS3-0 bit PLL PLL3-0 bit AK4631 BICK
16fs
: BICK or FCK pin BICK 7.35kHz 26kHz 7.35kHz 48kHz FCK (See Table 6)
AK4631
MCKO MCKI BICK FCK SDTO SDTI 16fs, 32fs, 64fs 1fs BCLK FCK SDTI SDTO
DSP or P
Figure 19. PLL Slave Mode 1 (PLL Reference Clock: FCK or BICK pin) b) PLL MCKO : MCKI pin BICK, FCK MCKO FCK FS3-0 bit
11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz
(See Table 5)
AK4631
MCKI MCKO BICK FCK SDTO SDTI 256fs 16fs, 32fs, 64fs 1fs
DSP or P
MCLK BCLK FCK SDTI SDTO
Figure 20. PLL Slave Mode 2 (PLL Reference Clock: MCKI pin) ADC or DAC PMADC bit = "1" or PMDAC bit = "1" (MCKI, BICK, FCK) PMADC bit = PMDAC bit = "0"
MS0317-J-01 - 26 -
2004/11
ASAHI KASEI
[AK4631]
EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") PMPLL bit "0" ADC, DAC MCKI pin PLL CODEC I/F MCKI (256fs, 512fs or 1024fs), BICK (32fs), FCK(fs) MCKI MCKI FS3-0 bit See Table 10 Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don't care 0 256fs 0 7.35kHz fs 48kHz Don't care 1 1024fs 0 7.35kHz < fs 13kHz Don't care 0 256fs 1 7.35kHz < fs 48kHz Don't care 1 512fs 1 7.35kHz < fs 26kHz Table 10. EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") MCKI Mode 0 DAC S/N S/N Table 11 DAC MCKI AOUT FS3-2 bits FS1 bit FS0 bit (EXT Mode)
FCK
Default
EXT Slave Mode
S/N
S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 11. Relationship between MCKI and S/N of AOUT MCKI ADC or DAC PMADC bit = "1" or PMDAC bit = "1" (MCKI, BICK, FCK) PMADC bit = PMDAC bit = "0"
AK4631
MCKO 256fs, 512fs or 1024fs MCKI BICK FCK SDTO SDTI 32fs, 64fs 1fs MCLK BCLK FCK SDTI SDTO
DSP or P
Figure 21. EXT Slave Mode
MS0317-J-01 - 27 -
2004/11
ASAHI KASEI
[AK4631]
4
(Table 12) FCK BICK ""
DIF1-0 bit
MSB
2's
Mode 1-3 Mode 0 1 2 3
SDTO DIF1 0 0 1 1
BICK DIF0 0 1 0 1
SDTI
BICK
"" Figure See Table 11 Figure 26 Figure 27 Figure 28
SDTO (ADC) DSP Mode
BICK 16fs 32fs 32fs I2S I2S 32fs Table 12. Audio Interface Format I/F SDTI SDTI BICK BICK BICK "" ""
SDTI (DAC) DSP Mode
Default
Mode 0 (DSP BCKP bit = "0" BCKP bit = "1" MSBS bit
)
BCKP, MSBS bit SDTO SDTO BICK BICK "" ""
SDTO/SDTI
MSB
MSBS bit BCKP bit Audio Interface Format 0 0 Figure 22 0 1 Figure 23 1 0 Figure 24 1 1 Figure 25 Table 13. Audio Interface Format in Mode 0 ADC "-1" 128 8bit "-256" 16bit "-1" 8bit 8bit 8bit 16bit "-1" 16bit 16bit 16bit
DAC
PDN pin AK4631 PMADC bit "0" "1" 1059/fs=133ms@fs=8kHz ADC
"L"
ADC ADC 2's "0" DAC
MS0317-J-01 - 28 -
2004/11
ASAHI KASEI
[AK4631]
FCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BICK(16fs) SDTO(o) SDTI(i)
15
0 0
15 14 15 14
8
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
15 14 15 14
8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
15 15
0
1
2
8
14
15
16
17
18
29
30
31
0
1
2
8
8
9
10
11
12
13
30
31
0
BICK(32fs) SDTO(o) SDTI(i)
15 14 15 14 8 2 2 1 1 0 0 15 14 15 14 8 8 2 2 1 1 0 0
Don't Care
Don't Care
1/fs 15:MSB, 0:LSB
1/fs
Figure 22. Mode 0 Timing (BCKP = "0", MSBS = "0")
FCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BICK(16fs) SDTO(o) SDTI(i)
15
0 0
15 14 15 14
8
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
15 14 15 14
8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
15 15
0
1
2
8
14
15
16
17
18
29
30
31
0
1
2
8
8
9
10
11
12
13
30
31
0
BICK(32fs) SDTO(o) SDTI(i)
15 14 15 14 8 2 2 1 1 0 0 15 14 15 14 8 8 2 2 1 1 0 0
Don't Care
Don't Care
1/fs 15:MSB, 0:LSB
1/fs
Figure 23. Mode 0 Timing (BCKP = "1", MSBS = "0")
MS0317-J-01 - 29 -
2004/11
ASAHI KASEI
[AK4631]
FCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BICK(16fs) SDTO(o) SDTI(i)
15
0 0
15 14 15 14
8
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
15 14 15 14
8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
15 15
0
1
2
8
14
15
16
17
18
29
30
31
0
1
2
8
8
9
10
11
12
13
30
31
0
BICK(32fs) SDTO(o) SDTI(i)
15 14 15 14 8 2 2 1 1 0 0 15 14 15 14 8 8 2 2 1 1 0 0
Don't Care
Don't Care
1/fs 15:MSB, 0:LSB
1/fs
Figure 24. Mode 0 Timing (BCKP = "0", MSBS = "1")
FCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BICK(16fs) SDTO(o) SDTI(i)
15
0 0
15 14 15 14
8
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
15 14 15 14
8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
15 15
0
1
2
8
14
15
16
17
18
29
30
31
0
1
2
8
8
9
10
11
12
13
30
31
0
BICK(32fs) SDTO(o) SDTI(i)
15 14 15 14 8 2 2 1 1 0 0 15 14 15 14 8 8 2 2 1 1 0 0
Don't Care
Don't Care
1/fs 15:MSB, 0:LSB
1/fs
Figure 25. Mode 0 Timing (BCKP = "1", MSBS = "1")
MS0317-J-01 - 30 -
2004/11
ASAHI KASEI
[AK4631]
FCK
0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTO(o) SDTI(i)
0
15 14 13 15 14 13
1 2 3
8
7 7
14
6 6
15
5 5
16
4 4
17
3 3
18
2 2
1 1
31
0 0
0 1 2 3 14
15 15
18 31 0 1
Don't Care
15 16 17
BICK(64fs) SDTO(o) SDTI(i)
15 14 13 2 1 0 15
Don't Care 15:MSB, 0:LSB Data
15 14
1
0
Don't Care
1/fs
Figure 26. Mode 1 Timing
FCK
0 1 2 8 9 10 11 12 13 14 15 0 1 2 8 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTO(o) SDTI(I)
0
15 14
8
7
6
5
4
3
2
1
0
15
15 14
1 2 3
8
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0 1 2 3 14
Don't Care
14 15 16 17 18 31 0
15
1
BICK(64fs) SDTO(o) SDTI(i)
15 14 13 13 2 1 0 15
15 14 13
13 2
1
0
Don't Care
Don't Care
15
15:MSB, 0:LSB Data 1/fs
Figure 27. Mode 2 Timing
MS0317-J-01 - 31 -
2004/11
ASAHI KASEI
[AK4631]
FCK
0 1 2 3 4 9 10 11 12 13 14 15 0 1 2 3 4 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTO(o) SDTI(i)
0 1
15 14 13 15 14 13
2 3 4
7
7 7
14 15
6 6
16
5 5
17
4 4
18
3 3
2 2
31
1 1
0
0 0
1 2 3 4 14 15 16 17 18 31 0 1
BICK(64fs) SDTO(o) SDTI(i)
15 14 13 15 14 13 2 1 0
2
1
0
Don't Care
Don't Care
15:MSB, 0:LSB
Data 1/fs
Figure 28. Mode 3 Timing
HPF
ADC DC HPF (fs) HPF 0.62Hz (@fs=8kHz)
AK4631 typ. 30k MGAIN1 bit 0 0 1 1
MGAIN1-0 bits
MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 14. Input Gain
Default
MPI pin min. 2k
MPI pin
MIC Power MPI pin
(0.75 x AVDD)V (typ) (Figure 29 )
2k Microphone MIC pin MIC-Amp
Figure 29. MIC Block Circuit MS0317-J-01 - 32 2004/11
ASAHI KASEI
[AK4631]
AK4631 1. 2.
ALC1 bit = "0" ALC1 ZTM1-0, LMTH ALC1
3. IPGA IPGA6-0 bits ZTM1-0 bits IPGA6-0 bit
MIC - ALC
ALC1 bit = "1" [1] ALC1 ALC1 ATT ZELM bit="1" LMTH ZELM bit="0" IPGA [2] ALC1 ALC1 WTM1-0 bit (REF6-0 bit) IPGA WTM1-0 bit ALC1 ZTM1-0 bit ALC1 IPGA ALC1 WTM1-0 bit WTM1-0 bit ALC1 ZTM1-0 bit IPGA (LMAT1-0 bit) LTM1-0 bit ALC1 bit "0" ALC1 IPGA IPGA (LMTH) ALC1 ALC1 ALC
LMTH IPGA
ALC1 ALC1 ALC1 ( (
IPGA
ALC1
(LMTH)
) )>
IPGA IPGA
<(
)
ALC1
ALC
MS0317-J-01 - 33 -
2004/11
ASAHI KASEI
[AK4631]
[3] ALC1 Table 15 ALC1 Comment ALC1 0dB fs=8kHz Operation -4dBFS Don't use Enable 16ms fs=16kHz Data Operation 1 -4dBFS 00 Don't use 0 Enable 01 16ms 01 47H 10H 00 0 1 16ms +27.5dB 0dB 1 step 1 step Enable
Register Name LMTH LTM1-0 ZELM ZTM1-0 WTM1-0 REF6-0 IPGA6-0 LMAT1-0 RATT ALC1
Limiter detection Level Limiter operation period at ZELM = 1 Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data 00 16ms as ZTM1-0 bits Maximum gain at recovery operation 47H +27.5dB IPGA gain at the start of ALC1 operation 10H 0dB Limiter ATT Step 00 1 step Recovery GAIN Step 0 1 step ALC1 Enable bit 1 Enable Table 15. Examples of the ALC1 setting
Data 1 00 0 00
ALC1 ALC1 bit = "0" or PMMIC bit = "0" LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM ALC1 = "1" "0" PMMIC bit = "0" IPGA PMMIC bit = "1" IPGA6-0 bits ALC1 ALC1 bit = "0" IPGA
Example:
ALC1
IPGA6-0 bit ALC1 bit
Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 1 Maximum Gain = +27.5dB Limiter Detection Level = -4dBFS Manual Mode ALC2 bit = "1" (default) (1) Addr=06H, Data=00H
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (REF6-0)
(2) Addr=08H, Data=47H
WR (IPGA6-0)
* The value of IPGA should be the same or smaller than REF's
(3) Addr=09H, Data=10H
WR (ALC1= "1", LMAT1-0, RATT, LMTH, ZELM)
(4) Addr=07H, Data=61H
ALC1 Operation
Note : WR : Write Figure 30. Registers set-up sequence at ALC1 operation
MS0317-J-01 - 34 -
2004/11
ASAHI KASEI
[AK4631]
AK4631 MUTE DAC 1061/fs
0.5dB 256/fs
256 +12dB
-115dB DVTM bit
DVOL7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB * * 18H 0dB Default * * FDH -114.5dB FEH -115.0dB FFH MUTE (-) Table 16. Digital Volume Code Table
DVTM bit 0 1
DVOL7-0 bits 00H FFH fs=8kHz 1061/fs 133msec 256/fs 32msec Table 17.
fs=22.05kHz 48msec 12msec
BEEP
PMBP bit = "1" BEEPA bit "1" Ri BEEPS bit "1" BEEP pin Ri = 20k Table 18 BEEP Ri
Rf Ri BEEP
+
Figure 31. Block Diagram of BEEP pin
SPKG1-0 bits 00 01 10 11
SPP/SPN +7.89dB +9.93dB +14.11dB +16.15dB Table 18. Ri = 20k
BEEP
BEEP
AOUT 0dB 0dB 0dB 0dB
BEEP
MS0317-J-01 - 35 -
2004/11
ASAHI KASEI
[AK4631]
(AOUT pin)
DAC min. 10k "1" DACA bit "0" PMAO bit = AOPSN bit = "0" AOPSN bit = "1" PMAO bit ON/OFF Figure 32 C AOPSN bit = "0" AOUT OFF AVSS ON/OFF 20k C=1F PMAO bit = "1" 300 ms 100k(typ) AOPSN bit =
1F AOUT
220
20k
Figure 32. AOUT
(
)
AOUT
(AK4631
(2 )
)
(5 )
P M A O b it (1 ) A O P S N b it (3 ) (4 ) (6 )
A O U T p in 300 m s
N o r m a l O u tp u t 300 m s
Figure 33. (1) (2) AOUT pin (3) AOUT pin AOUT (4) (5) AOUT pin (6) AOUT pin ON
AOUT
AOPSN bit = "1" PMAO bit = "1" C = 1F 200 ms(max 300ms) AOPSN bit = "0"
ON
AOPSN bit = "1" PMAO bit = "1" C = 1F 200 ms(max 300ms) AOPSN bit = "0"
MS0317-J-01 - 36 -
2004/11
ASAHI KASEI
[AK4631]
SVDD (50 DAC BTL SVDD, SPKG1-0 bits ) 2.6V ALC2
2.6V 3.6V
5.25V
SPKG1-0 bits AVDD SPKG1-0 bits ALC2
ALC2 OFF ALC2 ON SVDD AVDD,
SPKG1-0 bits 00 0dB 01 +2.04dB 10 +6.22dB 11 +8.26dB (Note) SPKG1-0bits= "00" Table 19. ALC2 OFF SPK-Amp ALC2 OFF SPK-Amp ALC2 ON DAC -0.5dBFS SPK-Amp 3.09Vpp, 150mW@8 3.09Vpp, 150mW@8 3.92Vpp, 240mW@8 3.92Vpp, 240mW@8 6.34Vpp (Note) 8.02Vpp (Note) 3.09Vpp 3.92Vpp 6.34Vpp 6.34Vpp 8.02Vpp 8.02Vpp DAC -0.5dBFS DVOL DAC
SPKG1-0 bits 00 01 10 11 00 01 10 11 (Note) SPK-Amp
AVDD 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
SVDD 3.3V 3.3V 3.3V 3.3V 5.0V 5.0V 5.0V 5.0V
3.92Vpp Table 20 SPK-Amp
30pF SPN pin Figure 34 GND
Figure 34
(10
) SPP pin,
SVDD 92% Ex) SVDD = 5.0V
(Figure 34 ZD) : 4.6V ZD 5.3V 5.1V(Min 4.97V, Max
SVDD+0.3V 5.24V)
MS0317-J-01 - 37 -
2004/11
ASAHI KASEI
[AK4631]
ZD
SPK-Amp
SPP
10
SPN 10 ZD
Figure 34. SPK
(
)
PMSPK bit "0"
(MOUT, ALC2, SPK-AMP) MOUT, SPP, SPN pin Hi-Z
Power-up/down
PMSPK bit
PMSPK bit "1" SPPS bit "0" SPP pin Hi-Z SPN pin SVDD/2 PDN pin "L" "H" SPP pin PMSPK bit "1" SPN pin SVDD/2 Power-down SPP, SPN pin (PMSPK bit="0")
Hi-Z
PMSPK bit
SPPS bit
SPP pin
Hi-Z
Hi-Z
SPN pin
Hi-Z
SVDD/2
SVDD/2
Hi-Z
>t1(Note)
>0
Figure 35. Power-up/Power-down Timing for Speaker-Amp (Note) "t1" MIN pin MIN-Amp (ALC2) MOUT pin - MIN pin SPK-Amp
Enable
: t1 = 5 = 18ms Ex) MOUT pin - MIN pin =0.1 F, MIN pin 36k(Max) MOUT pin - MIN pin MIN pin (Rin) HPF (fc) fc = 66Hz@Rin=24k(typ), 133Hz@Rin=12k(min), 44Hz@Rin=36k(max)
MS0317-J-01 - 38 -
2004/11
ASAHI KASEI
[AK4631]
SPK - ALC
ALC2 bit = "1" ALC2 (MIN pin) typ. 24k VCOM Figure 36 ~ Figure 39 ALC2 "1", SVDD=5V) -7.1dBV 0.5dB ALC2 ALC2 SVDD=5V) -9.1dBV -7.1dBV PMSPK bit "0" ALC2 "1" ALC2 "-2dB" SVDD ALC2 ALC ALC2 ALC2
-7.1dBV(@SPKG1 bit = "0", SVDD=3.3V SPKG1 bit = ALC2 ALC2 250s (=2/fs@fs=8kHz)
1dB ALC2 -9.1dBV(@SPKG1 bit = "0", SVDD=3.3V SPKG1 bit = "1", ALC2 RFS5-0 bits ALC2 (512/fs=64ms @ fs=8kHz, ROTM bit = "0") ALC2 "-3.5dB " ROTM bit RFS5-0 bits PMSPK = "0"
ALC2 Disable (MIN SPP/SPN)
ALC2 Table 22
-3.5dB
ALC2 -9.1dBV fs=8kHz 512/fs = 64ms fs=16kHz 512/fs = 32ms (Timeout=512/fs) 0.5dB step 1dB step ATT/GAIN Table 21. Limiter /Recovery of ALC2 (ROTM bit = "0") SPKG1-0 bits 00 +4.4dB 01 +6.4dB 10 +10.6dB 11 +12.7dB Table 22. ALC2 OFF SPK-Amp(Full-differential
ALC2 -7.1dBV 2/fs = 250s 2/fs = 125s
)
MS0317-J-01 - 39 -
2004/11
ASAHI KASEI
[AK4631]
0.8dBV -3.1dBV -3.1dBV -4.0dB -8dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV +6.0dB +14.0dB -8dB -23.1dBV +7.9dB FS-4.0dB = -7.1dBV
0dBV
-1.2dBV +7.9dB -5.2dBV Full-differential Single-ended
FS
+1.9dB
-10dBV
FS-12dB
-15.1dBV
-15.1dBV
-20dBV
-30dBV DVOL DAC
ALC2 SPK-AMP
(AVDD=3.3V, SVDD=3.3V, DVOL=-8.0dB/0dB, SPKG1-0 bit = "00",) * FS = Full Scale Figure 36. Speaker-Amp Output Level Diagram
10dBV
Full-differential 0.8dBV +9.9dB -3.2dBV -4.0dB -8dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV -15.1dBV -15.1dBV +6.0dB +14.0dB -8dB -23.1dBV +3.9dB
2.8dBV FS-4dB = -7.1dBV -3.1dBV -3.1dBV +9.9dB
0dBV
Single-ended
FS
-10dBV
FS-12dB
-20dBV
-30dBV DVOL DAC
ALC2 SPK-AMP
(AVDD=3.3V, SVDD=3.3V, DVOL=-8.0dB/0dB, SPKG1-0 bit = "01",) * FS = Full Scale Figure 37. Speaker-Amp Output Level Diagram
MS0317-J-01 - 40 -
2004/11
ASAHI KASEI
[AK4631]
10dBV
7.0dBV +14.1dB +14.1dB -3.1dBV -3.1dBV FS-4dB = -7.1dBV -4.0dB -8dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV -15.1dBV -15.1dBV +6.0dB +14.0dB -8dB -23.1dBV +8.1dB 5.0dBV 1.0dBV Full-differential Single-ended
0dBV FS
-10dBV
FS-12dB
-20dBV
-30dBV DVOL DAC
ALC2 SPK-AMP
(AVDD=3.3V, SVDD=5.0V, DVOL=-8.0dB/0dB, SPKG1-0 bit = "10",) * FS = Full Scale Figure 38. Speaker-Amp Output Level Diagram
10dBV
7.1dBV 3.1dBV
9.1dBV +16.2dB +16.2dB
Full-differential
Single-ended
0dBV
-3.1dBV -3.1dBV
FS
-8dB
FS-4dB = -7.1dBV -4.0dB +2.0dB
+10.2dB
-10dBV
FS-6.0dB = -9.1dBV
-11.1dBV
FS-12dB
-15.1dBV
-15.1dBV
+6.0dB +14.0dB
-8dB
-20dBV
-23.1dBV
-30dBV DVOL DAC
ALC2 SPK-AMP
(AVDD=3.3V, SVDD=5.0V, DVOL=-8.0dB/0dB, SPKG1-0 bit = "11",) * FS = Full Scale Figure 39. Speaker-Amp Output Level Diagram
MS0317-J-01 - 41 -
2004/11
ASAHI KASEI
[AK4631]
(2bits, "10"
3 I/F pin(CSN, CCLK, CDTI) I/F Chip address ), Read/Write (1bit; "1" ), Register address (MSB first, 5bits) Control Data (MSB first, 8bits) CCLK "" "" CSN "" CCLK 5MHz (max) PDN pin="L"
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK CDTI
C1 C0 R/W A4 A3 A2 A2 A0 D7 D6 D5 D4 D3 D2 D1 D0 "1" "0" "1"
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (C1 = "1", C0 = "0"); Fixed to "10" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data
Figure 40. Serial Control I/F Timing
MS0317-J-01 - 42 -
2004/11
ASAHI KASEI
[AK4631]
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH
Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Input PGA Control Digital Volume Control ALC2 Mode Control
D7 0 0 SPPS 0 PLL3 0 DVTM 0 0 0 DVOL7 0
D6 PMVCM 0 BEEPS AOPSN PLL2 0 ROTM ALC2 REF6 IPGA6 DVOL6 0
D5 PMBP 0 ALC2S MGAIN1 PLL1 FS3 ZTM1 ALC1 REF5 IPGA5 DVOL5 RFS5
D4 PMSPK 0 DACA SPKG1 PLL0 MSBS ZTM0 ZELM REF4 IPGA4 DVOL4 RFS4
D3 PMAO M/S DACM SPKG0 BCKO1 BCKP WTM1 LMAT1 REF3 IPGA3 DVOL3 RFS3
D2 PMDAC MCKPD MPWR BEEPA BCKO0 FS2 WTM0 LMAT0 REF2 IPGA2 DVOL2 RFS2
D1 PMMIC MCKO MICAD ALC1M DIF1 FS1 LTM1 RATT REF1 IPGA1 DVOL1 RFS1
D0 PMADC PMPLL MGAIN0 ALC1A DIF0 FS0 LTM0 LMTH REF0 IPGA0 DVOL0 RFS0
PDN pin = "L" resets the registers to their default values. Note: "0" Note: "1" 00H 0BH
MS0317-J-01 - 43 -
2004/11
ASAHI KASEI
[AK4631]
Addr 00H
Register Name Power Management 1 Default
D7 0 0
D6 PMVCM 0
D5 PMBP 0
D4 PMSPK 0
D3 PMAO 0
D2 PMDAC 0
D1 PMMIC 0
D0 PMADC 0
PMADC: ADC 0: Power down (Default) 1: Power up PMADC bit "0"
"1" ADC
(1059/fs=133ms@fs=8kHz)
PMMIC: (MIC-Amp, ALC1) 0: Power down (Default) 1: Power up PMDAC: DAC 0: Power down (Default) 1: Power up PMAO: 0: Power down (Default) 1: Power up PMSPK: 0: Power down (Default) 1: Power up PMBP: 0: Power down (Default) 1: Power up PMBP bit = "0" BEEPS bit = "0" bit = "0" PMVCM: VCOM 0: Power down (Default) 1: Power up ON/OFF ("1"/"0") PDN pin "L"
BEEP BEEP BEEPA
00H
PMPLL
MCKO IPGA IPGA6-0 bit PMVCM bit "1" 00H PMPLL
"0"
PMVCM bit MCKO
"0" "0" BEEP
AOUT BEEP ADC, DAC, ALC1, ALC2
MS0317-J-01 - 44 -
2004/11
ASAHI KASEI
[AK4631]
Addr 01H
Register Name Power Management 2 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 M/S 0
D2 MCKPD 1
D1 MCKO 0
D0 PMPLL 0
PMPLL: PLL 0: EXT Mode and Power Down (Default) 1: PLL Mode and Power up MCKO: MCKO 0: "L" Output (Default) 1: 256fs Output MCKPD: MCKI pin 0: Master Clock input enable 1: Pull down by 25k(typ.) (Default) M/S: Master / Slave Mode 0: Slave Mode (Default) 1: Master Mode
MS0317-J-01 - 45 -
2004/11
ASAHI KASEI
[AK4631]
Addr 02H
Register Name Signal Select 1 Default
D7 SPPS 0
D6 BEEPS 0
D5 ALC2S 0
D4 DACA 0
D3 DACM 0
D2 MPWR 0
D1 MICAD 0
D0
MGAIN0
1
MGAIN1-0: MGAIN 1 bit 03H D6 bit
(See Table 23)
MGAIN1 bit 0 0 1 1
MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 23. Input Gain
Default
MICAD: ADC 0: OFF (Default) 1: ON "1" ALC1 MPWR: MIC 0: OFF (Default) 1: ON PMMIC bit ="1" DACM: DAC 0: OFF (Default) 1: ON PMSPK bit="1"
ALC1
ADC
PMSPK bit="0"
MOUT pin
Hi-Z
DACA: DAC 0: OFF (Default) 1: ON PMAO bit="1"
PMAO bit="0"
AOUT pin
AVSS
ALC2S: 0: OFF (Default) 1: ON "1" ALC2 BEEPS: BEEP pin 0: OFF (Default) 1: ON "1" BEEP
ALC2
SPPS: 0: Power Save Mode (Default) 1: Normal Operation "0" PMSPK bit ="1" PMSPK bit ="0"
SPP pin
Hi-Z SPN pin SVDD/2 PDN pin="L"
MS0317-J-01 - 46 -
2004/11
ASAHI KASEI
[AK4631]
Addr 03H
Register Name Signal Select 2 Default
D7 0 0
D6 AOPSN 0
D5
MGAIN1
0
D4 SPKG1 0
D3 SPKG0 0
D2 BEEPA 0
D1 ALC1M 0
D0 ALC1A 0
ALC1A: 0: OFF (Default) 1: ON PMAO bit="1"
ALC1
PMAO bit="0"
AOUT pin
AVSS
ALC1M: 0: OFF (Default) 1: ON PMSPK bit="1"
ALC1
PMSPK bit="0"
MOUT pin
Hi-Z
BEEPA: 0: OFF (Default) 1: ON PMAO bit="1"
BEEP
PMAO bit="0"
AOUT pin
AVSS
SPKG1-0:
(See Table 24) SPKG1-0 bits 00 0dB 01 +2.2dB 10 +4.4dB 11 +8.7dB Table 24. SPK-Amp
MGAIN1:
(See Table 23)
ALC1M
IPGA
ALC2S DACM
MIX
ALC2
SPK
DAC
BEEPS
BEEP
ALC1A DACA
AOUT
BEEPA
Figure 41. Speaker and Mono Lineout-Amps switch control
MS0317-J-01 - 47 -
2004/11
ASAHI KASEI
[AK4631]
AOPSN: (AOUT pin) 0: Normal Operation (Default) 1: Power Save Mode "1" (See Figure 33)
Addr 04H Register Name Mode Control 1 Default D7 PLL3 0 D6 PLL2 0 D5 PLL1 0 D4 PLL0 0 D3 BCKO1 0 D2 BCKO0 0
PMAO bit
D1 DIF1 1
D0 DIF0 0
DIF1-0: Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO (ADC) DSP Mode
(See Table 25) BICK 16fs 32fs 32fs I2S I2S 32fs Table 25. Audio Interface Format (See Table 26) SDTI (DAC) DSP Mode Figure See Table 31 Figure 26 Figure 27 Figure 28
Default
BCKO1-0: Mode 0 1 2 3
BICK
BCKO0 BCKO1 BICK 0 0 16fs 0 1 32fs 1 0 64fs 1 1 N/A Table 26. BICK Output Frequency at Master Mode (See Table 27)
Default
PLL3-0: PLL
Mode
0 1 2 3 4 5 6 7 12 13
Others
PLL3 bit 0 0 0 0 0 0 0 0 1 1
PLL Reference Input Clock Input Pin Frequency FCK pin 1fs BICK pin 16fs BICK pin 32fs BICK pin 64fs MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz Others N/A Table 27. Setting of PLL Mode (*fs: Sampling Frequency)
PLL2 bit 0 0 0 0 1 1 1 1 1 1
PLL1 bit 0 0 1 1 0 0 1 1 0 0
PLL0 bit 0 1 0 1 0 1 0 1 0 1
Default
MS0317-J-01 - 48 -
2004/11
ASAHI KASEI
[AK4631]
Addr 05H
Register Name Mode Control 2 Default
D7 0 0
D6 0 0
D5 FS3 0
D4 MSBS 0
D3 BCKP 0
D2 FS2 0
D1 FS1 0
D0 FS0 0
FS3-0: PLL
(See Table 28 and Table 29)
MCKI EXT
(See Table 30) MCKI
Mode 0 1 2 3 4 5 6 7 10 11 14 15 Others
Sampling Frequency 8kHz Default 12kHz 16kHz 24kHz 7.35kHz 11.025kHz 14.7kHz 22.05kHz 32kHz 48kHz 29.4kHz 44.1kHz Others N/A Table 28. Setting of Sampling Frequency at PLL2 bit = "1" and PMPLL bit = "1"
FS3 bit 0 0 0 0 0 0 0 0 1 1 1 1
FS2 bit 0 0 0 0 1 1 1 1 0 0 1 1
FS1 bit 0 0 1 1 0 0 1 1 1 1 1 1
FS0 bit 0 1 0 1 0 1 0 1 0 1 0 1
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 Don't care 0 0 0 Default 7.35kHz fs 8kHz 0 Don't care 1 1 0 8kHz < fs 12kHz 0 Don't care 0 2 1 12kHz < fs 16kHz 0 Don't care 1 3 1 16kHz < fs 24kHz 1 Don't care 0 6 1 24kHz < fs 32kHz 1 Don't care 1 7 1 32kHz < fs 48kHz Others Others N/A Table 29. Setting of Sampling Frequency Range at PLL2 bit = "0" and PMPLL bit = "1"
Mode 0 1 2 3
MCKI Input Frequency Don't care 0 256fs 0 Don't care 1 1024fs 0 Don't care 0 256fs 1 Don't care 1 512fs 1 Table 30. EXT Slave Mode (PMPLL bit = "0", M/S bit = "0")
FS3-2 bits
FS1 bit
FS0 bit
Sampling Frequency Range 7.35kHz fs 48kHz 7.35kHz < fs 13kHz 7.35kHz < fs 48kHz 7.35kHz < fs 26kHz MCKI
Default
BCKP, MSBS: "00" (Default) (See Table 31) MSBS bit BCKP bit Audio Interface Format 0 0 Figure 22 0 1 Figure 23 1 0 Figure 24 1 1 Figure 25 Table 31. Audio Interface Format in Mode 0
Default
MS0317-J-01 - 49 -
2004/11
ASAHI KASEI
[AK4631]
Addr 06H
Register Name Timer Select Default
D7 DVTM 0
D6 ROTM 0
D5 ZTM1 0
D4 ZTM0 0
D3 WTM1 0
D2 WTM0 0
D1 LTM1 0
D0 LTM0 0
LTM1-0: ALC1 ALC1 IPGA "00" LTM1 LTM0
(see Table 32) Disable (ZELM bit="1")
ALC1 LTM1-0 bit
IPGA
ALC1 8kHz 16kHz 0 0 0.5/fs Default 63s 31s 0 1 1/fs 125s 63s 1 0 2/fs 250s 125s 1 1 4/fs 500s 250s Table 32. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit="1") WTM1-0: ALC1 ALC1 "00" WTM1 0 0 1 1 WTM0 (see Table 33)
ALC1 8kHz 16kHz 0 128/fs 16ms 8ms 1 256/fs 32ms 16ms 0 512/fs 64ms 32ms 1 1024/fs 128ms 64ms Table 33. ALC1 Recovery Operation Waiting Period (see Table 34) ALC1 "00"
Default
ZTM1-0: ALC1
ZTM1 0 0 1 1
ZTM0
8kHz 0 128/fs 16ms 1 256/fs 32ms 0 512/fs 64ms 1 1024/fs 128ms Table 34. Zero Crossing Timeout Period
16kHz 8ms 16ms 32ms 64ms
Default
ROTM: ALC2 0: 512/fs (Default) 1: 1024/fs ROTM bit DVTM : Digital Volume 0: 1061/fs (Default) 1: 256/fs
PMSKP bit = "0"
DVOL7-0 bits
00H
FFH
MS0317-J-01 - 50 -
2004/11
ASAHI KASEI
[AK4631]
Addr 07H
Register Name ALC Mode Control 1 Default
D7 0 0
D6 ALC2 1
D5 ALC1 0
D4 ZELM 0
D3 LMAT1 0
D2 LMAT0 0
D1 RATT 0
D0 LMTH 0
LMTH: ALC1 ALC1 ( 2dB) LMTH 0 1
/ "0"
(see Table 35)
ALC1 ALC1 ADC Input -6.0dBFS -6.0dBFS > ADC Input -8.0dBFS ADC Input -4.0dBFS -4.0dBFS > ADC Input -6.0dBFS Table 35. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 36) IPGA 30H RATT bit="1" 1dB (=0.5 x 2) (REF6-0 bit)
Default
RATT: ALC1 ALC1 IPGA IPGA
ALC1 IPGA
IPGA
32H
RATT GAIN STEP 0 1 Default 1 2 Table 36. ALC1 Recovery Gain Step Setting LMAT1-0: ALC1 ATT ALC1 IPGA LMAT1-0 bit="11" (=0.5 x 4) ALC1 IPGA="00H" (see Table 37) ALC1 ALC1 LTM1-0 bit ZELM bit "00H" (LMTH) IPGA IPGA 43H 47H 2dB
LMAT1 LMAT0 ATT STEP 0 0 1 Default 0 1 2 1 0 3 1 1 4 Table 37. ALC1 Limiter ATT Step Setting ZELM: ALC1 0: Enable (Default) 1: Disable "0" ALC1 "1" ALC1
IPGA ALC1 IPGA
MS0317-J-01 - 51 -
2004/11
ASAHI KASEI
[AK4631]
ALC1: ALC1 0: ALC1 Disable (Default) 1: ALC1 Enable "1" ALC1
"0"(Disable)
ALC2: ALC2 0: ALC2 Disable 1: ALC2 Enable (Default) (512/fs=64ms@fs=8kHz, ROTM bit = "0") ALC2 PDN pin "L" "H" PMSPK bit "0" "1"(Enable)
"1"
Addr 08H
Register Name ALC Mode Control 2 Default
D7 0 0
D6 REF6 0
D5 REF5 1
D4 REF4 1
D3 REF3 0
D2 REF2 1
D1 REF1 1
D0 REF0 0
REF6-0: ALC1 ALC1
IPGA
(see Table 38) REF6-0 bit IPGA IPGA 30H 2FH + 2step "36H"
= 31H
REF=30H, RATT=2 step, IPGA=2FH REF=30H
DATA (HEX) GAIN (dB) STEP 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 Default : : 10 +0.0 : : 0.5dB 06 -5.0 05 -5.5 04 -6.0 03 -6.5 02 -7.0 01 -7.5 00 -8.0 Table 38. Setting Reference Value at ALC1 Recovery Operation
MS0317-J-01 - 52 -
2004/11
ASAHI KASEI
[AK4631]
Addr 09H
Register Name Input PGA Control Default
D7 0 0
D6 IPGA6 0
D5 IPGA5 0
D4 IPGA4 1
D3 IPGA3 0
D2 IPGA2 0
D1 IPGA1 0
D0 IPGA0 0
IPGA6-0:
PGA (see Table 39) "10H" IPGA PMMIC bit = "1" PMMIC bit = "1" 2/fs (250s@fs=8kHz) IPGA PMMIC bit = "0" ALC1 bit "1" "0" IPGA ALC1 IPGA ZTM1-0 bit IPGA IPGA
ALC1 bit = "0" IPGA
DATA (HEX) GAIN (dB) STEP 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 : : 10 +0.0 : : 0.5dB 06 -5.0 05 -5.5 04 -6.0 03 -6.5 02 -7.0 01 -7.5 00 -8.0 Table 39. Input Gain Setting
Addr 0AH Register Name D7 DVOL7 0 D6 DVOL6 0 D5 DVOL5 0 D4 DVOL4 1
Default
Digital Volume Control
Default
D3 DVOL3 1
D2 DVOL2 0
D1 DVOL1 0
D0 DVOL0 0
DVOL7-0: AK4631
MUTE
0.5dB DAC
(see Table 40) 256 +12dB 1061/fs (= 133ms @ fs = 8kHz) DVTM bit
(DVOL) -115dB 256/fs (= 32ms @ fs = 8kHz)
DVOL7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB * * 18H 0dB Default * * FDH -114.5dB FEH -115.0dB FFH MUTE (-) Table 40. Digital Volume Code Table
MS0317-J-01 - 53 -
2004/11
ASAHI KASEI
[AK4631]
Addr 0BH
Register Name ALC2 Mode Control Default
D7 0 0
D6 0 0
D5 RFS5 1
D4 RFS4 1
D3 RFS3 1
D2 RFS2 1
D1 RFS1 0
D0 RFS0 0
RFS6-0: ALC2
(see Table 41) REFS5-0 bits Volume[dB] Step 3F +19.5 3E +19.0 3D +18.5 3C +18.0 Default : : 0.5dB 19 +0.5 18 +0.0 17 -0.5 : : 03 -10.5 02 -11.0 01 -11.5 00 -12.0 Table 41. Setting Reference Value at ALC2 Recovery Operation
MS0317-J-01 - 54 -
2004/11
ASAHI KASEI
[AK4631]
Figure 42
C 2.2k 1 MPI 28 MIC 27 0.22 R MICOUT 26 AIN 25 BEEP 24 20k 220 1 AOUT 23 MOUT 22 0.1
(AKD4631)
+ 2.2
0.1 0.1 Cp Rp
1 VCOM 2 AVSS 3 AVDD 4 VCOC 5 PDN 6 CSN 7 CCLK
MIN 21 0.1 SVSS 20 SVDD 19 + R2 R1 10
Analog Supply 2.63.6V
10
+
Analog Supply 2.65.25V
Speaker
Top View
SPN 18 SPP 17 MCKO 16 MCKI 15 13 DVDD
ZD2
ZD1
Dynamic SPK : R1,R2 : Short ZD1,ZD2 : Open Peizo SPK : R1,R2 : 10 ZD1,ZD2 : Required
10 SDTO
14 DVSS 0.1 10
10
12 BICK
8 CDTI
9 SDTI
11 FCK
+
DSP or P
Figure 42. Typical Connection Diagram : - AK4631 AVSS, DVSS, SVSS - BEEP pin R C - EXT (PMPLL bit = "0") VCOC pin - PLL (PMPLL bit = "1") VCOC pin Cp Rp Table 42 - MICOUT-AIN AIN HPF typ. 72Hz (min. 48Hz, max. 145Hz) PLL3 bit 0 0 0 0 0 0 0 0 1 1 PLL2 bit 0 0 0 0 1 1 1 1 1 1
Others
0.22F
Mode
PLL1 bit 0 0 1 1 0 0 1 1 0 0
PLL0 bit 0 1 0 1 0 1 0 1 0 1
PLL
0 1 2 3 4 5 6 7 12 13
Others
FCK pin 1fs BICK pin 16fs BICK pin 32fs BICK pin 64fs MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz N/A Table 42. Setting of PLL Mode (*fs: Sampling Frequency)
VCOC pin Rp,Cp Rp[] Cp[F] 6.8k 220n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n
PLL (max) 160ms 2ms 2ms 2ms 40ms 40ms 40ms 40ms 40ms 40ms
Default
MS0317-J-01 - 55 -
2004/11
ASAHI KASEI
[AK4631]
1. AVDD, DVDD, SVDD AVDD, DVDD, SVDD AVSS, DVSS, SVSS PC
2. VCOM 0.1F AVSS VCOM pin VCOM pin 2.2F
3. BEEP 0.06 x AVDD Vpp(typ) (typ: 0.45 x 0.6 x AVDD Vpp(typ) fc=1/(2RC) AK4631 AVSS AVDD
AVDD) DC
4. DAC 8000H(@16bit) SVDD/2 2's 0000H(@16bit) 0.45 x AVDD (typ) 7FFFH(@16bit) VCOM
VCOM
MS0317-J-01 - 56 -
2004/11
ASAHI KASEI
[AK4631]
ADC, DAC, ALC1, ALC2, IPGA
1. PLL
Power Supply
Example:
(1)
PDN pin
(2) (3)
PMVCM bit
(Addr:00H, D6) (4)
Audio I/F Format: DSP Mode, BCKP = MSBS = "0" BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO : Enable Sampling Frequency:8kHz
MCKPD bit
(Addr:01H, D2) (5)
(1) Power Supply & PDN pin = "L"
"H"
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0) (6)
(2)Addr:01H, Data:0CH Addr:04H, Data:48H Addr:05H, Data:00H
Input
MCKI pin
M/S bit
(Addr:01H, D3) 40msec(max) (7)
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0BH
Output
BICK pin FCK pin
(8) 1msec (max)
MCKO, BICK and FCK output
40msec(max) (10)
MCKO pin
(9)
Output
Figure 43. Clock Set Up Sequence (1) < (1) > PDN pin "L" "H" (1) AK4631 150ns "L" (2) DIF1-0, PLL3-0, FS2-0, BCKO1-0, MSBS, BCKP, M/S bit (3) VCOM PMVCM bit = "0" "1" VCOM (4) MCKI pin : MCKPD bit = "1" "0" (5) MCKO : MCKO bit = "1" MCKO : MCKO bit = "0" (6) PMPLL bit "0" "1" MCKI pin PLL 40ms(max) (7) PLL BICK, FCK pin (8) FCK BICK (9) MCKO pin (10) PLL MCKO pin
PLL
MS0317-J-01 - 57 -
2004/11
ASAHI KASEI
[AK4631]
2. PLL
(FCK or BICK pin)
Power Supply
(1)
Example:
Audio I/F Format : DSP Mode, BCKP = MSBS = "0" PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz
(2) (3)
PDN pin PMVCM bit
(Addr:00H, D6)
4fs ofPower Supply & PDN pin = "L" (1)
(4) "H"
"H"
MCKPD bit
(Addr:01H, D2)
(2) Addr:04H, Data:30H Addr:05H, Data:00H
PMPLL bit
(Addr:01H, D0)
(3) Addr:00H, Data:40H
FCK pin BICK pin Internal Clock
(6)
Input
(5)
(4) Addr:01H, Data:05H
BICK and FCK input
Figure 44. Clock Set Up Sequence (2) < (1) > PDN pin "L" "H" AK4631 150ns "L" (2) DIF1-0, FS2-0, PLL3-0, MSBS, BCKP bit (3) VCOM PMVCM bit = "0" "1" VCOM (4) MCKI pin : MCKPD bit = "1" (5) PMPLL bit "0" "1" PLL FCK or BICK pin PLL PLL FCK PLL 160ms(max), BICK PLL 2ms(max) (6) PLL (1)
MS0317-J-01 - 58 -
2004/11
ASAHI KASEI
[AK4631]
3. PLL
(MCKI pin)
Example:
Power Supply
(1)
Audio I/F Format: DSP Mode, BCKP = MSBS = "0" BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO : Enable Sampling Frequency:8kHz
(2) (3)
PDN pin PMVCM bit
(Addr:00H, D6) (4)
(1) Power Supply & PDN pin = "L"
"H"
MCKPD bit
(Addr:01H, D2) (5)
MCKO bit
(Addr:01H, D1)
(2)Addr:01H, Data:04H Addr:04H, Data:48H Addr:05H, Data:00H
PMPLL bit
(Addr:01H, D0) (6)
(3)Addr:00H, Data:40H
Input
40msec(max) (7)
MCKI pin
(4)Addr:01H, Data:03H
Output
(9)
MCKO pin
(8)
MCKO output start
BICK pin FCK pin
Input
BICK and FCK input start
Figure 45. Clock Set Up Sequence (3) < (1) (1) > PDN pin "L" "H" AK4631 150ns "L" (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP, M/S bit (3) VCOM PMVCM bit = "0" "1" VCOM (4) MCKI pin : MCKPD bit = "1" "0" (5) MCKO : MCKO bit = "1" (6) PMPLL bit "0" "1" MCKI pin PLL 40ms(max) (7) PLL MCKO pin (8) MCKO pin (9) MCKO BICK, FCK
PLL
MS0317-J-01 - 59 -
2004/11
ASAHI KASEI
[AK4631]
4.
(
)
Example
Power Supply
(1)
Audio I/F Format:MSB justified (ADC and DAC) Input MCKI frequency: 1024fs Sampling Frequency:8kHz MCKO: Disable
PDN pin
(2) (3)
(1) Power Supply & PDN pin = "L"
"H"
PMVCM bit
(Addr:00H, D6)
MCKPD bit
(Addr:01H, D2) (4)
(2) Addr:04H, Data:02H Addr:05H, Data:01H
PMPLL bit
(Addr:01H, D0) "L" (5)
(3) Addr:00H, Data:40H
MCKI pin
(5)
Input
(4) Addr:01H, Data:00H
FCK pin BICK pin
Input
MCKI, BICK and FCK input
Figure 46. Clock Set Up Sequence (4) < (1) (1) > PDN pin "L" "H" AK4631 150ns "L" (2) DIF1-0, FS1-0 bit (3) VCOM PMVCM bit = "0" "1" VCOM (4) MCKI pin : MCKPD bit = "1" "0" PLL : PMPLL bit = "0" (5) MCKI, FCK, BICK
MS0317-J-01 - 60 -
2004/11
ASAHI KASEI
[AK4631]
Example:
FS3-0 bits
(Addr:05H, D5,D2-0)
XXXX
(1)
XXX
PLL Master Mode Audio I/F Format:DSP Mode, BCKP=MSBS="0" Sampling Frequency:8kHz Pre MIC AMP:+20dB MIC Power On ALC1 setting:Refer to Figrure 29 ALC2 bit="1"(default)
MIC Control
(Addr:02H, D2-0)
001
(2)
X1X 00H
(3)
(1) Addr:05H, Data:00H
ALC1 Control 1
(Addr:06H)
XXH XXH
(4)
(2) Addr:02H, Data:07H
ALC1 Control 2
(Addr:08H)
47H
(3) Addr:06H, Data:00H
ALC1 Control 3
(Addr:07H)
XXH
(5)
61H or 21H ALC1 Enable ALC1 Disable
(4) Addr:08H, Data:47H
ALC1 State PMADC bit
(Addr:00H, D0)
ALC1 Disable
(5) Addr:07H, Data:61H
(6) Addr:00H, Data:43H
(6) (7) 1059 / fs
PMMIC bit
(Addr:00H, D1)
Recording
ADC Internal State
Power Down
Initialize Normal State Power Down
(7) Addr:00H, Data:40H
Figure 47. MIC Input Recording Sequence < > fs=8kHz ALC1 sequence at ALC1 operation"
ALC1
"Figure 30. Registers set-up
(1)
(FS3-0 bit) PLL PLL (6) ADC (2) ( 02H) (3) ALC1 Timer 06H (4) ALC1 REF 08H (5) LMTH, RATT, LMAT1-0, ALC1 bit 07H (6) ADC : PMMIC bit = PMADC bit = "0" "1" ADC 1059/fs=133ms@fs=8kHz ALC1 bit "1"
ALC1 IPGA
(0dB)
(7) ADC ALC1 ALC1 Disable (ALC1 bit = "0") PMMIC bit = "0"
: PMMIC bit = PMADC bit = "1" "0" ALC1 bit "1" ALC1 PMMIC bit = "0" IPGA
MS0317-J-01 - 61 -
2004/11
ASAHI KASEI
[AK4631]
Example:
FS3-0 bits
(Addr:05H, D5,D2-0)
XXXX
(1)
XXXX
(8)
PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= "0" Sampling Frequency: 8kHz Digital Volume: -8dB ALC2 : Enable
DACM bit
(Addr:02H, D3) (2)
(1) Addr:05H, Data:00H
ALC2S bit
(Addr:02H, D5)
(2) Addr:02H, Data:28H
ALC2 bit
(Addr:07H, D6)
0
(3)
X XXXXXXX
(4) (9)
(3) Addr:07H, Data:40H
DVOL7-0 bits
(Addr:0AH, D7-0)
0001100
(4) Addr:0AH, Data:28H
PMDAC bit
(Addr:00H, D2) (5)
(5) Addr:00H, Data:54H
PMSPK bit
(Addr:00H, D4) (6)
(6) Addr:02H, Data:A8H
SPPS bit
(Addr:02H, D7) (7)
Playback
SPP pin SPN pin Hi-Z
Hi-Z SVDD/2
Normal Output Normal Output
Hi-Z SVDD/2 Hi-Z
(7) Addr:02H, Data:28H
(8) Addr:00H, Data:40H
Figure 48. Speaker-Amp Output Sequence < (1) > (FS3-0 bit) PLL PLL (5) DAC (2) DAC SPK-Amp DACM = ALC2S bit: "0" "1" (3) ALC2 (ALC2bit) (4) ( 0AH) DAC Default (0dB) (5) DAC : PMDAC bit = PMSPK bit = "0" "1" ALC2 bit = "1" (512/fs =64ms (@fs=8kHz, ROTM bit = "0") ALC2 ALC2 "-2dB " ALC2 "-2dB" (6) (6) MIN pin MIN-Amp (ALC2) : SPPS bit = "0" "1" MIN pin - MOUT pin SPK-Amp
Enable 5 = 18ms
e.g. Input Impedance of MIN pin =36k (max), C=0.1F : (7) : SPPS bit = "1" "0" (8) DAC SPK-Amp Disable DACM = ALC2S bit: "1" "0" (9) DAC : PMDAC bit = PMSPK bit = "1" "0"
MS0317-J-01 - 62 -
2004/11
ASAHI KASEI
[AK4631]
BEEP
CLOCK ALC2 bit
(Addr:07H, D6)
Clocks can be stopped.
Example: (1) Addr:07H, Data:00H
0 or 1
(1)
0
PMBP bit
(Addr:00H, D2) (2) (6)
(2) Addr:00H, Data:70H
PMSPK bit
(Addr:00H, D4)
(3) Addr:02H, Data:60H
ALC2S bit
(Addr:02H, D5)
0 or 1
(3)
0
(7)
(4) Addr:02H, Data:E0H
BEEPS bit
(Addr:02H, D6) (4)
BEEP Signal Output
SPPS bit
(Addr:02H, D7) (5)
(5) Addr:02H, Data:60H
SPP pin SPN pin Hi-Z
Hi-Z SVDD/2
Normal Output Normal Output
Hi-Z
(6) Addr:00H, Data:40H
SVDD/2
Hi-Z
(7) Addr:02H, Data:00H
Figure 49. "BEPP-Amp < > "BEEP-Amp SPK-Amp" Disable
Speaker-Amp" Output Sequence
ALC2
(1) ALC2 Disable: ALC2 bit = "0" (2) BEEP-Amp PMBP bit = PMSPK bit = "0" "1" (3) ALC2 SPK-Amp Disable: ALC2S bit = "0" BEEP SPK-Amp Enable: BEEPS bit = "0" "1" (4) : SPPS bit = "0" "1" (4) BEEP pin SPK-Amp Enable e.g. R=20k, C=0.1F : 5 = 10ms (5) : SPPS bit = "1" "0" (6) BEEP-Amp : PMBP bit = PMSPK bit = "1" "0" (7) BEEP SPK-Amp Disable: BEEPS bit = "1" "0"
BEEP-Amp
MS0317-J-01 - 63 -
2004/11
ASAHI KASEI
[AK4631]
1.
(AK4536/AK4630
)
Example:
PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= "0" Sampling Frequency: 8kHz Digital Volume: -8dB
FS3-0 bits
(Addr:05H, D5,D2-0)
XXXX
(1)
XXXX
(1) Addr:05H, Data:00H
(6) (2) (3)
DACA bit
(Addr:02H, D4)
(2) Addr:02H, Data:10H
DVOL7-0 bits
(Addr:0AH, D7-0)
00011000
XXXXXXX
(3) Addr:0AH, Data:28H
PMDAC bit
(Addr:00H, D2) (4) (5)
(4) Addr:00H, Data:4CH
PMAO bit
(Addr:00H, D3)
Playback
AOUT pin
Hi-Z
Normal Output
Hi-Z
(5) Addr:00H, Data:40H
(6) Addr:02H, Data:00H
Figure 50. Mono Lineout Sequence < (1) > (FS3-0 bit) PLL (4) DAC (2) DAC DACA bit: "0" "1" (3) ( 0AH) DAC Default (4) DAC DAC (5) DAC DAC (6) DAC DACA bit: "1" "0" Disable PLL
(0dB) : PMDAC bit = PMAO bit = "0" "1" AOUT pin : PMDAC bit = PMAO bit = "1" "0" AOUT pin
MS0317-J-01 - 64 -
2004/11
ASAHI KASEI
[AK4631]
2. AK4631
Example:
PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= "0" Sampling Frequency: 8kHz Digital Volume: -8dB MGAIN1=SPKG1=SPKG0=BEEPA=ALC1M =ALC1A= "0"
(1) Addr:05H, Data:00H (2) Addr:02H, Data:10H
FS3-0 bits
(Addr:05H, D5, D2-0)
XXXX
(1)
XXXX
(9)
(3) Addr:0AH, Data:28H (4) Addr:03H, Data:40H
DACA bit
(Addr:02H, D4)
(2) (3)
DVOL7-0 bits
(Addr:0AH, D7-0)
(5) Addr:00H, Data:4CH
XXXXXXX
00011000
(6) Addr:03H, Data:00H
AOPSN bit
(Addr:03H, D6) (4) (6) (7) (10)
Playback (7) Addr:03H, Data:40H
PMDAC bit
(Addr:00H, D2) (5) >300 ms >300 ms (8)
PMAO bit
(Addr:00H, D3)
(8) Addr:00H, Data:40H
Normal Output
AOUT pin
(9) Addr:02H, Data:00H (10) Addr:03H, Data:00H
Figure 51. Mono Lineout Sequence < (1) PLL (2) DAC (3) DAC (4) AOUT (5) DAC AOUT pin (6) AOUT AOUT (7) AOUT (8) DAC AOUT pin (9) DAC (10) AOUT AOUT > (FS3-0 bit) (5) DAC DACA bit: "0" "1" ( 0AH) Default (0dB) AOPSN bit: "0" "1" : PMDAC bit = PMAO bit = "0" "1" C = 1F max 300ms AOPSN bit: "1" "0" AOUT pin AOPSN bit: "0" "1" : PMDAC bit = PMAO bit = "1" "0" C = 1F max 300ms Disable DACA bit: "1" "0" AOPSN bit: "1" "0"
MS0317-J-01 - 65 -
2004/11
ASAHI KASEI
[AK4631]
ADC, DAC, ALC1, ALC2, IPGA
3. PLL
Example:
(1)
PMPLL bit
(Addr:01H,D0) (2)
Audio I/F Format: DSP Mode, BCKP = MSBS = "0" BICK frequency at Master Mode : 64fs Input Master Clock Select at PLL Mode : 11.2896MHz Sampling Frequency:8kHz
MCKO bit
(Addr:01H,D1)
"H" or "L" (3)
(1) (2) (3) Addr:01H, Data:0CH Stop an external MCKI
(4)
MCKPD bit
(Addr:01H,D2)
External MCKI
Input
Figure 52. Clock Stopping Sequence (1) < > (1) PLL (2) MCKO (3) MCKI pin MCKI pin (4) : PMPLL bit = "1" "0" : MCKO bit = "1" "0" : MCKPD bit = "0" "1" Hi-Z MCKI pin
4. PLL,
(FCK, BICK pin)
Example
(1)
PMPLL bit
(Addr:01H,D0) (2)
Audio I/F Format : DSP Mode, BCKP = MSBS = "0" PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz
External BICK External FCK
Input
(2)
(1) Addr:01H, Data:04H
Input
(2) Stop the external clocks
Figure 53. Clock Stopping Sequence (2) < > (1) PLL (2) : PMPLL bit = "1" "0"
MS0317-J-01 - 66 -
2004/11
ASAHI KASEI
[AK4631]
5. PLL
(MCKI pin)
(1)
PMPLL bit
(Addr:01H,D0) (1)
MCKO bit
(Addr:01H,D1) (1)
Example
Audio I/F Format : DSP Mode, BCKP = MSBS = "0" PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz
MCKPD bit
(Addr:01H,D2) (2)
(1) Addr:01H, Data:04H
External MCKI
Input
(2) Stop the external clocks
Figure 54. Clock Stopping Sequence (3) < > (1) PLL : PMPLL bit = "1" "0" MCKO : MCKO bit = "1" "0" MCKI pin : MCKPD bit = "0" "1" MCKI pin Hi-Z (2)
MCKI pin
6.
Example
(1)
MCKPD bit
(Addr:01H,D2) (2)
Audio I/F Format :MSB justified(ADC and DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz
External MCKI External BICK External FCK
Input
(2)
(1) Addr:01H, Data:04H
Input
(2)
(2) Stop the external clocks
Input
Figure 55. Clock Stopping Sequence (4) < > (1) MCKI pin MCKI pin (2)
: MCKPD bit = "0" "1" Hi-Z MCKI pin
VCOM PDN pin = "L"
MS0317-J-01 - 67 -
2004/11
ASAHI KASEI
[AK4631]
* 28pin QFN (Unit: mm)
0. 55 20 0. 4-
5.2 0.20 5.0 0.10
5.2 0.20
5.0 0.10
M
0.21 0.05
0.05
Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate (Pb free)
MS0317-J-01 - 68 -
0.02 +0.03
-0.02
0.80 +0.20
-0.10
0. C 6
2 0. 5 0. 10
28
1 0.22 0.05 0.50 0.05
0.60 0.10
2004/11
ASAHI KASEI
[AK4631]
4631
XXXXX
1
XXXXX : Date code identifier (5 )
Date (YY/MM/DD) 04/06/15 04/11/19
Revision 00 01
Reason
Page P4-6 P8
Contents "AK4536 AK4630 : Speaker-Amp "Note 6. 8 = 2.6V 3.6V " Note 6 SVDD
*
* * *
* *
MS0317-J-01 - 69 -
2004/11

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